Clock Jitter Attenuators

Our clock jitter attenuators generate infinite combinations of low jitter output frequencies from any input frequency. Based on our innovative third generation wireless DSPLL® architecture, these devices simplify clock tree design by replacing multiple clocks and oscillators and minimizing bill of materials count and complexity.

Frequency range
2 kHz to 1.4 GHz
Ultra-low jitter
300 fs RMS

Clock Jitter Attenuator Common Specs

  • Generates any frequency on any output (2 kHz to 1.4 GHz)
  • Ultra-low jitter: 300 fs RMS
  • Integrated loop filter with selectable loop bandwidth
  • Hitless switching with phase buildout (auto/manual)
  • Synchronous and freerun modes
  • Best-in-class PSRR
  • Dynamically reconfigurable output frequency (per output)
  • Fast-lock < 100 ms


Find the Right General Purpose Jitter Attenuator Select Columns
Select Columns
Part Number Number of Inputs Number of Outputs Input Frequency Min Input Frequency Max Output Frequency Min Output Frequency Max Output Format(s) Description Phase Jitter (RMS) VDD (V) VDDO (V) Package Type Package Size (mm) Synchronous Ethernet/1588 Intel x86 Clocks

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