LVDS Buffers

Our LVDS clock buffers are low jitter non-PLL based fanout buffers delivering best-in-class performance, minimal cross-talk, and superior supply noise rejection. Devices are available in industrial and automotive grade2 temperature ranges. With additive jitter as low as 50 fs RMS, our LVDS buffers deliver up to 10 output clocks from DC to 1250 MHz.

Up to 10
Low additive jitter
50 fs RMS

LVDS Buffer Common Specs

  • Up to 10 differential LVDS outputs
  • Provides signal level translation
  • Loss of Signal (LOS) indicator allows system clock monitoring
  • Wide operating frequency DC - 1.25 GHz
  • Accepts any differential or single-ended input
  • Glitchless clock switching
  • Synchronous and individual output enable control options available
  • Integrated voltage level translation
  • Selectable drive strength to tailor jitter/EMI performance
  • Loss of Signal (LOS) indicator
  • Low output-output skew: < 50 ps
  • Excellent PSRR
  • Independent VDD and VDDO: 1.8, 2.5, or 3.3 V
  • Automotive Grade2, -40 to +105 °C
  • AECQ-100 qualified options


Find the Right LVDS Buffer Select Columns
Select Columns
Part Number Number of Inputs Number of Outputs Frequency Min (MHz) Frequency Max Output Format(s) Additive Jitter VDD (V) VDDO (V) Package Type Package Size (mm) Universal Buffers Differential Buffers LVCMOS Buffers PCIe Compliant Zero Delay Buffers Automotive

Sort A -> Z
Sort Z -> A

Filter by values...

Loading Results