HSTL Buffers

Our HSTL Clock Buffers are low jitter non-PLL based fanout buffers offering industry-leading flexibility while delivering best-in-class performance with additive jitter as low as 150 fs-rms. The family utilizes Silicon Laboratories' advanced CMOS technology to fanout 8 clocks from 5 - 350 MHz with guaranteed low additive jitter, low skew and low propagation delay variability. The family features HSTL output buffers with minimal cross-talk and superior supply noise rejection, simplifying low jitter clock distribution in noisy environments.

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HSTL Buffer Common Specs

Eight single-ended SSTL outputs
Provides signal level translation
Loss of Signal (LOS) indicator allows system clock monitoring

Output Enable (OEB) pin allows glitchless control of output clocks
Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V

Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V
Additive jitter: 150 fs RMS typ
Industrial temperature range:
- -40 to +85 °C

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Find the Right HSTL Buffer Select Columns

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Part Number	Number of Inputs	Number of Outputs	Frequency Min (MHz)	Frequency Max	Output Format(s)	Additive Jitter	VDD (V)	VDDO (V)	Package Type	Package Size (mm)	Universal Buffers	Differential Buffers	LVCMOS Buffers	PCIe Compliant	Zero Delay Buffers	Automotive

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HSTL Buffers

HSTL Buffer Common Specs

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