HCSL Buffer Common Specs
- Four differential HCSL outputs
- Provides signal level translation
- Loss of Signal (LOS) indicator allows system clock monitoring
- Output Enable (OEB) pin allows glitchless control of output clocks
- Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V
- Automotive Grade2, -40 to +105 °C
- AECQ-100 qualified options
- Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V
- Additive jitter: 150 fs RMS typ
- Industrial temperature range: -40 to +85 °C
Find the Right HCSL Buffer
Select Columns
| Part Number | Number of Inputs | Number of Outputs | Frequency Min (MHz) | Frequency Max | Output Format(s) | Additive Jitter | VDD (V) | VDDO (V) | Package Type | Package Size (mm) | Universal Buffers | Differential Buffers | LVCMOS Buffers | PCIe Compliant | Zero Delay Buffers | Single Ended Input | Automotive |
|---|
Sort A -> Z
Sort Z -> A
Filter by values...
For PCIe applications, please refer to our portfolio of low-power PCIe Gen1/2/3/4/5 fanout buffers that feature HCSL output drivers with internal termination.