CMOS Clock Buffers

Our CMOS clock buffers are low jitter, non-PLL based fanout buffers offering industry-leading flexibility while delivering best-in-class performance. The devices feature CMOS output buffers with minimal cross-talk and superior supply noise rejection, simplifying low-jitter clock distribution in noisy environments. CMOS clock buffers are available in industrial and automotive grade2 temperature ranges.

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CMOS Buffer Common Specs

Up to 12 single-ended CMOS, SSTL, HSTL outputs
Provides signal level translation
Loss of Signal (LOS) indicator allows system clock monitoring
Output Enable (OEB) pin allows glitchless control of output clocks

Wide operating frequency DC - 250 MHz
Glitchless clock switching
Synchronous and individual output enable control options available
Integrated voltage level translation

Automotive Grade2, -40 to +105 °C
AECQ-100 qualified options
Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5 or 3.3 V
Additive jitter: 150 fs RMS typ
Industrial temperature range: -40 to +85 °C

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Find the Right CMOS Buffer Select Columns

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Part Number	Number of Inputs	Number of Outputs	Frequency Min (MHz)	Frequency Max	Output Format(s)	Additive Jitter	VDD (V)	VDDO (V)	Package Type	Package Size (mm)	Universal Buffers	Differential Buffers	LVCMOS Buffers	PCIe Compliant	Zero Delay Buffers	Automotive

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CMOS Clock Buffers

CMOS Buffer Common Specs

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