Low Jitter and High Speed Clock Buffers in Any Format

Any Format Clock Buffers

Our low jitter clock buffers and level translators (Si533xx) deliver multiple output clock formats from any input clock format. The device flexibility reduces bill of materials complexity by allowing the same product to be used across multiple projects and platforms. Clock formats supported by the low jitter clock buffers and level translators include LVDS, LVPECL, CML, LVCMOS, SSTL, HCSL and HSTL.

Any Format Clock Buffer Common Specs

Pin-selectable signal format (LVPECL, low-power LVPECL, LVDS, CML, HCSL, LVCMOS)
Wide operating frequency DC - 1.25 GHz
2-10 differential or 4-20 LVCMOS outputs
Accepts any differential or single-ended input
Low additive jitter: 45 fs rms (12 kHz - 20 MHz) typical

Glitchless clock switching
Synchronous and Individual output enable control options available
Integrated voltage level translation
Selectable drive strength to tailor jitter/EMI performance

Loss of signal (LOS) indicator
Optional output clock division: div-1, div-2, div-4
Low output-output skew: <50 ps
Excellent PSRR
Independent VDD and VDDO: 1.8, 2.5 or 3.3 V

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Any Format Clock Buffers

Any Format Clock Buffer Common Specs

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