Silicon Labs “Triple-Play Timing Solutions for 56G SerDes”
- Ease the migration from 10G/28G to 56G
- Sub-100fs RMS phase jitter performance maximizes design margin
- Frequency flexible clocks integrate SerDes, CPU and system timing into single IC
- Only timing supplier offering comprehensive clock and oscillator portfolio for 56G
Jitter Attenuating Clocks
- 4 inputs, 12 outputs
- 69fs RMS phase jitter
- Hitless Reference Switching