Lower Cost, Smaller Footprint & Improved Jitter for Cloud Switch

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Timing

Customer's Needs

Minimize BOM cost
Easy to design
Meet stringent 10G jitter specs

Results

25% lower timing BOM cost
40% smaller PCB footprint
Meets 10G PHY jitter specs

Products

Situation:

A major manufacturer of Ethernet switches for internet infrastructure had been using a competitor’s clock generators for their “cloud” switches. The competing clock solution required a large PCB footprint and had difﬁculty meeting the jitter performance requirements for 10 Gigabit Ethernet while still providing all of the clock frequencies necessary for the design.

Solution:

An improved switch design using a single Si5341 ultra-low jitter clock generator and a Si53302 buffer allowed the customer to provide 9 low jitter clocks for 10 Gigabit Ethernet, along with multiple additional clock frequencies for other system components. To achieve the same results with the competitor’s solution, it would have been necessary to use 3 separate PLL chips. As a result, the Silicon Labs solution reduced the PCB footprint by 40% and lowered timing bill of materials costs by 25%. In addition, the system jitter performance was improved by 80% over the competition.

Benefit:

Designers and manufacturers beneﬁt from lower costs and faster time to market resulting from a simpler timing design. The improved jitter performance also alleviates concerns about system performance under varying ﬁeld conditions.

Clock Generator and Buffer Fundamentals:

Frequency Fexibility: Generates any frequency on any output 10 unique outputs per device
Ultra-Low Jitter: Si5341 Clock Generator: <100 fs RMS typical Si53302 Buffer: 45 fs RMS typical
Multi-format Output: Each output independently conﬁ gurable for LVPECL, LVDS, HCSL, LVCMOS, or CML standards, with independent power supply voltage pins
ClockBuilder Pro: Easy to use GUI simpliﬁes clock tree design and device conﬁguration